Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Cited by 39 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
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2. Suppression of buried oxide induced variability on digital performance of GeOI pMOSFETs using substrate bias scheme;Microsystem Technologies;2019-11-28
3. The formation mechanism of globally biaxial strain in He+ implanted silicon-on-insulator wafer based on the plastic deformation and smooth sliding of buried SiO2 film;Applied Physics Letters;2018-11-26
4. Simulation Analysis in Sub-0.1 μm for Partial Isolation Field-Effect Transistors;Electronics;2018-10-02
5. Enhancing digital performance of nanoscale GeOI MOSFETs through optimization of buried oxide properties and channel thickness;Microsystem Technologies;2018-09-11
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