Suppression of buried oxide induced variability on digital performance of GeOI pMOSFETs using substrate bias scheme
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s00542-019-04701-y.pdf
Reference31 articles.
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2. Asenov A, Kaya S, Davies JH, Saini S (2000) Oxide thickness variation induced threshold voltage fluctuations in decanano MOSFETs: a 3D density gradient simulation study. Superlattices Microstruct 28(5/6):507–515
3. Ernst T, Tinella C, Raynaud C, Cristoloveanu S (2002) Fringing fields in sub-0.1 µm fully depleted SOI MOSFETs: optimization of the device architecture. Solid-State Electron 46:373–378
4. Hellings G, Eneman G, Krom R, Jaeger BD, Mitard J, Keersgieter AD, Hoffmann T, Meuris M, Meyer KD (2010) Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans Electron Devices 57(10):2539–2546
5. Hutin L, Royer CL, Damlencourt J-F, Hartmann J-M, Grampeix H, Mazzocchi V, Tabone C, Previtali B, Pouydebasque A, Vinet M, Faynot O (2010) GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current. IEEE Electron Device Lett 31(3):234–236
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