Highly-Strained Silicon-On-Insulator Development

Author:

Akatsu Takeshi,Hartmann Jean-Michel,Aulnette Cécile,Le Vaillant Yves-Matthieu,Rouchon Denis,Abbadie Alexandra,Bogumilowicz Yann,Portigliatti Lionel,Colnat Cyrille,Boudou Nicolas,Lallement Fabrice,Triolet Fanny,Figuet Christophe,Martinez Muriel,Nguyen Phuong,Delattre Cécile,Tsyganenko Kira,Berne Cécile,Allibert Frédéric,Deguet Chrystel

Abstract

Bi-axially highly-strained Silicon-On-Insulator (sSOI) substrates with a tensile stress up to 2.5 GPa have been obtained by Smart CutTM technology. Thin strained silicon (sSi) layers epitaxially grown on relaxed Si0.6Ge0.4 virtual substrates (VS) were used as starting materials. The threading dislocation density in those sSi layers was in the low 105 cm-2. Some stacking faults were also present in those highly strained Si films. The evolution of this linear defect density was characterized as a function of the sSi thickness by Secco etch. 2.5 GPa sSOI wafers have been demonstrated in 200 mm diameter. Stress uniformity σ equal to 1.14% and 2 nm thickness range has been obtained for 8 nm thick sSi layers.

Publisher

The Electrochemical Society

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