A review of the mechanical stressors efficiency applied to the ultra-thin body & buried oxide fully depleted silicon on insulator technology

Author:

Morin Pierre,Maitrejean Sylvain,Allibert Frederic,Augendre Emmanuel,Liu Qing,Loubet Nicolas,Grenouillet Laurent,Pofelski Alexandre,Chen Kangguo,Khakifirooz Ali,Wacquez Romain,Reboh Shay,Bonnevialle Aurore,le Royer Cyrille,Morand Yves,Kanyandekwe Joel,Chanemougamme Daniel,Mignot Yann,Escarabajal Yann,Lherron Benoit,Chafik Fadoua,Pilorget Sonia,Caubet Pierre,Vinet Maud,Clement Laurent,Desalvo Barbara,Doris Bruce,Kleemeier Walter

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference107 articles.

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2. Ang KW, Chui KJ, Bliznetsov V, Du A, Balasubramanian N, Li MF, et al. Enhanced performance in 50nm N-MOSFETs with silicon–carbon source/drain regions. IEEE international electron devices meeting. IEDM technical digest; 2004. p. 1069–71. http://dx.doi.org/10.1109/IEDM.2004.1419383.

3. Ito S, Namba H, Yamaguchi K, Hirata T, Ando K, Koyama S, et al. Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design. International electron devices meeting. IEDM ’00 technical digest; 2000. p. 247–50. http://dx.doi.org/10.1109/IEDM.2000.904303.

4. Ootsuka F, Wakahara S, Ichinose K, Honzawa A, Wada S, Sato H, et al. A highly dense, high-performance 130nm node CMOS technology for large scale system-on-a-chip applications. International electron device meeting. IEDM ’00 technical digest; 2000. p. 575–8. http://dx.doi.org/10.1109/IEDM.2000.904385.

5. Yang HS, Malik R, Narasimha S, Li Y, Divakaruni R, Agnello P, et al. Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing. IEEE international electron devices meeting. IEDM technical digest; 2004, p. 1075–7. http://dx.doi.org/10.1109/IEDM.2004.1419385.

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