Author:
Lin Dennis,Waldron Niamh,Brammertz Guy,Martens Koen,Wang Wei-E,Sioncke Sonja,Delabie Annelies,Bender Hugo,Conard Thierry,Tseng W. H.,Lin J.C.,Temst Kristiaan,Vantomme Andre,Mitard Jerome,Caymax Matty,Meuris Marc,Heyns Marc,Hoffman Thomas
Abstract
A new passivation approach integrating the III-V/Ge MOSFET gate stack processes for a complete CMOS solution is proposed. We explore the In0.53Ga0.47As and Ge MOS electrical properties and present the common gate stack (CGS) concept based on the complementary nature of the asymmetric oxide-In0.53Ga0.47As and the oxide-Ge interface state distributions. In addition, this approach requires neither the interfacial passivation layer (IPL) such as Si, nor the native oxide such as the GeO2, between the gate dielectric and the channels. The oxide-semiconductor interface properties of the common gate stack III-V/Ge MOS system have been carefully investigated and MOS transistors have been fabricated to validate the proposed common gate stack concept. It has been demonstrated that the above common gate stack MOS system can achieve high-performance n-channel operation on In0.53Ga0.47As substrates and p-channel operation on Ge substrates.
Publisher
The Electrochemical Society
Cited by
15 articles.
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