High Efficiency Low Temperature Pre-epi Clean Method for Advanced Group IV epi Processing

Abstract

In the present paper we discuss an alternative pre-epi clean method, which is performed at a reduced temperature of 600ºC, while maintaining SiO2 removal efficiency of the conventional H2 pre-epi bake at 800-900ºC. It is essentially an ex-situ HF-dip followed by a GeH4-enhanced Si etch that is performed in-situ in an epi reactor. The etch process lifts-off residual SiO2 together with a very thin well controlled top layer of crystalline Si. An optimal combination of 1.5-1.6nm loss and O, C - free interface has been demonstrated on bare (100) Si wafers. Defect-free substrate-epi interface was verified by photoluminescence study. The amount of removed Si was found to depend on crystal orientation of exposed Si surface, (110) Si being etched ~3x faster than (100) Si. Therefore the method needs to be carefully optimized for devices with various surfaces exposed simultaneously.