Catalyst Assisted Low Temperature Pre Epitaxial Cleaning for Si and SiGe Surfaces
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Published:2014-09
Issue:
Volume:219
Page:16-19
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ISSN:1662-9779
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Container-title:Solid State Phenomena
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language:
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Short-container-title:SSP
Author:
Dhayalan Sathish Kumar1, Hikavyy Andriy1, Loo Roger1, Wostyn Kurt1, Kenis Karine1, Shimura Yosuke1, Rosseel Erik1, Profijt Harald B.2, Maes Jan Willem2, Douhard Bastien1, Vandervorst Wilfried1
Affiliation:
1. IMEC VZW 2. ASM Belgium
Abstract
Novel scaling approaches such as sGe channels on strain relaxed SiGe buffers, source/drain (S/D) stressors for FINFETs are usually grown using epitaxial process. Prior to the epitaxial growth, the starting surface should be free from oxygen and organic impurities. If not, these impurities would act as nucleating centres for defect formation resulting in defective epi growth. Conventionally, the wafers are HF dipped and then subjected to in-situ hydrogen bake at a temperature of 800°C in order to remove the above said impurities present on the wafer surface [1]. However, subjecting the strain relaxed SiGe to such high temperature baking would lead to roughening/islanding and subjecting the fins to high temperature baking might result in severe surface reflow [2]. As a result, the device performance would be adversely affected.
Publisher
Trans Tech Publications, Ltd.
Subject
Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics
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