Catalyst Assisted Low Temperature Pre Epitaxial Cleaning for Si and SiGe Surfaces

Abstract

Novel scaling approaches such as sGe channels on strain relaxed SiGe buffers, source/drain (S/D) stressors for FINFETs are usually grown using epitaxial process. Prior to the epitaxial growth, the starting surface should be free from oxygen and organic impurities. If not, these impurities would act as nucleating centres for defect formation resulting in defective epi growth. Conventionally, the wafers are HF dipped and then subjected to in-situ hydrogen bake at a temperature of 800°C in order to remove the above said impurities present on the wafer surface [1]. However, subjecting the strain relaxed SiGe to such high temperature baking would lead to roughening/islanding and subjecting the fins to high temperature baking might result in severe surface reflow [2]. As a result, the device performance would be adversely affected.