SiGe S/D Integration and Device Verification

Author:

Wang Guilei

Publisher

Springer Singapore

Reference41 articles.

1. Thompson S, Anand N, Armstrong M, Auth C, Arcot B, Alavi M et al. (2002) A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell. In: International electron devices meeting, 2002. IEDM’02, pp 61–64

2. Mistry K, Armstrong M, Auth C, Cea S, Coan T, Ghani T et al (2004) Delaying forever: uniaxial strained silicon transistors in a 90 nm CMOS technology. In: Symposium on VLSI technology 2004, pp 50–51

3. Thompson S, Sun G, Wu K, Lim J, Nishida T (2004) Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs. In: IEEE international electron devices meeting, 2004. IEDM Technical Digest, 2004, pp 221–224

4. Ghani T, Armstrong M, Auth C, Bost M, Charvat P, Glass G et al (2003) A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: IEEE international electron devices meeting, 2003. IEDM’03 Technical Digest, 2003, pp 11.6. 1–11.6. 3

5. Bai P, Auth C, Balakrishnan S, Bost M, Brain R, Chikarmane V et al (2004) A 65 nm logic technology featuring 35 nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm 2 SRAM cell. In: IEEE international electron devices meeting, 2004. IEDM Technical Digest, 2004, pp 657–660

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