Design of a novel low power 8-transistor 1-bit full adder cell

Author:

Wei Yi,Shen Ji-zhong

Publisher

Zhejiang University Press

Subject

General Engineering

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Optimizing Leakage Current and Fluctuations at Ground Rail in 1-bit 8T Full Adder Circuit Using Various MTCMOS Techniques;2022 4th International Conference on Inventive Research in Computing Applications (ICIRCA);2022-09-21

2. Analysis of Full Adder cells in Numerous Logic Styles;2022 International Conference on Electronics and Renewable Systems (ICEARS);2022-03-16

3. A new low-power Dynamic-GDI full adder in CNFET technology;Integration;2022-03

4. Performance Analysis and Comparison of Low Power Various Full Adder Circuits;Communications in Computer and Information Science;2021

5. Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design;Lecture Notes in Electrical Engineering;2021

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