Analysis of Full Adder cells in Numerous Logic Styles-Reference-Cited by-同舟云学术

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Analysis of Full Adder cells in Numerous Logic Styles

Published:2022-03-16 Issue: Volume: Page:
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Container-title:2022 International Conference on Electronics and Renewable Systems (ICEARS)
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Author:

Murugan K.¹,Nithya R.²,Prasanth K.³,Fowjiya S.²,Mageswari R. Uma⁴,Mohamed Ali E. A.⁵

Affiliation:

1. Bannari Amman Institute of Technolgy,Department of ECE,Sathyamangalam,Tamilnadu,India

2. Vivekananda College of Engineering for Women,Department of CSE,Tiruchengode,Tamilnadu,India

3. K.S. Rangasamy College of Technology,Department of IT,Tiruchengode,Tamilnadu,India

4. Vardhaman College of Engineering,Department of CSE,Hyderabad,Telangana,India

5. JP College of Engineering,Department of ECE,Tenkasi,Tamilnadu,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9751779/9751722/09751808.pdf?arnumber=9751808

Reference15 articles.

1. Performance metrics analysisof 4 bit array multiplier circuit using 2 pascl logic;rahma;IEEE Trans Ind,2014

2. Design of a novel low power 8-transistor 1-bit full adder cell;wei;J Zhejiang Univ -Sci C,2011

3. A novel low power multiplexer-based full adder cell

4. Low-power and high-performance 1-Bit CMOS full-adder cell;navi;J Comput,2008

5. LECTOR: a technique for leakage reduction in CMOS circuits

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