Design of Low-Power 10-Transistor Full Adder Using GDI Technique for Energy-Efficient Arithmetic Applications
Author:
Funder
DST Fist Fund
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-022-02287-x.pdf
Reference35 articles.
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3. I. Alamand, K.T. Lau, Approximate adder for low-power computations. Int. J. Electron. Lett. 5(2), 158–165 (2017)
4. M. Amini-Valashani, M. Ayat, S. Mirzakuchaki, Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder. Microelectronics J. 74, 49–59 (2018)
5. G.D. Basava Raj, M. Kusuma, G. Vijay Goud, G. Srinivasa Rao, Implementation of low power one-bit full adder with cadence tool. Mater. Today Proc. (2021). https://doi.org/10.1016/j.matpr.2021.02.185
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