Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design-Reference-Cited by-同舟云学术

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Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design

Published:2021 Issue: Volume: Page:117-126
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Saladi Krishna,Leela Kumari B.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-8439-8_10

Reference9 articles.

1. Goel S, Kumar A, Bayoumi MA (2006) Design of robust, energy-efficient full adders for deep-sub micrometer design using hybrid-CMOS logic style. IEEE Trans Very Large-Scale Integr (VLSI) Syst 14(12):1309–1321

2. Tajasob S, Rezaalipour M, Dehyadegari M (2019) Designing energy-efficient imprecise adders with multi-bit approximation. Microelectron J 89:41–55

3. Rakesh S, Vijula Grace KS (2019) A comprehensive review on the VLSI design performance of different parallel prefix adders. Mater Today Proc

4. Sunil Gavaskar Reddy Y, Rajendra Prasad VVGS (2011) Power comparison of CMOS and adiabatic full adder circuits. Int J VLSI Des Commun Syst (VLSICS) 2(3)

5. Wei Y, Shen J-Z (2011) Design of a novel low power 8-transistor 1-bit full adder cell. J Zhejiang Univ Sci C 12(7):604–607

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic;2023 26th International Conference on Computer and Information Technology (ICCIT);2023-12-13

2. Comparative Analysis of a Proposed Low-Power Adiabatic NOR Gate;2023 26th International Conference on Computer and Information Technology (ICCIT);2023-12-13

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