Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic-Reference-Cited by-同舟云学术

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Analysis of a Low-Power Full Adder and Half Adder Using a New Adiabatic Logic

Published:2023-12-13 Issue: Volume: Page:
ISSN:
Container-title:2023 26th International Conference on Computer and Information Technology (ICCIT)
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Author:

Ganguly Chamak¹,Meem Mazeda Zafor²,Kifayat Kabir S.M³,Biswas Satyendra N.⁴

Affiliation:

1. Primeasia University,Dept. of EEE,Dhaka,Bangladesh

2. Ahsanullah University of Science and Technology,Dept. of EEE,Dhaka,Bangladesh

3. ULKASEMI Pvt. Limited,Circuit and System Design,Dhaka,Bangladesh

4. Bloomsburg University,Dept.of EEE, AUST, Dhaka, Bangladesh and Dept. of BiCEP,PA,USA,17815

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10440723/10440967/10441271.pdf?arnumber=10441271

Reference11 articles.

1. Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design

2. Adiabatic logic: An alternative approach to low power application circuits

3. Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

4. Design and Analysis of a New Ultra Low Power Adiabatic VLSI Circuit;Ganguly;Journal of VLSI Design and Signal Processing,2023

5. Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design;International Journal of Advanced Research in Science, Communication and Technology;2024-09-03

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