Single lithography exposure edge placement model-Reference-Cited by-同舟云学术

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Single lithography exposure edge placement model

Published:2015-03-18 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
Short-container-title:

Author:

Tyminski Jacek K.

Publisher

SPIE

Reference8 articles.

1. Double patterning process with freezing technique;Wakamatsu,2009

2. Evaluation of double-patterning techniques for advanced logic nodes;Koay,2010

3. 32nm logic patterning options with immersion lithography;Lai,2008

4. Achieving overlay budgets for double patterning;Hazelton,2009

5. Scanner-dependent Optical Proximity Effects;Tyminski,2009

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. E-Test Validation of Space Error Budget and Metrology;IEEE Transactions on Semiconductor Manufacturing;2022-08

2. Robustness of interactive pattern fidelity error as a quality metric for integrated patterning;Advances in Patterning Materials and Processes XXXVI;2019-03-25

3. Pattern uniformity control in integrated structures;SPIE Proceedings;2017-03-27

4. Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography;Journal of Micro/Nanolithography, MEMS, and MOEMS;2016-04-27

5. Characterization and mitigation of relative edge placement errors (rEPE) in full-chip computational lithography;SPIE Proceedings;2015-10-23

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