Characterization and mitigation of relative edge placement errors (rEPE) in full-chip computational lithography

Author:

Sturtevant John,Gupta Rachit,Shang Shumay,Liubich Vlad,Word James

Publisher

SPIE

Reference20 articles.

1. Full-chip two-layer CD and overlay process window analysis;Gupta,2015

2. Mathematical and CAD Framework for proximity correction;Cobb,1996

3. Considerations for the use of defocus models in OPC;Sturtevant,2005

4. OPC to improve lithographic process window;Word,2006

5. Improving yield through the application of process window OPC;Azpiroz,2009

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Real-time full-wafer design-based inter-layer virtual metrology;Metrology, Inspection, and Process Control for Microlithography XXXIV;2020-03-20

2. Overlay error statistics for multiple-exposure patterning;Journal of Micro/Nanolithography, MEMS, and MOEMS;2019-04-04

3. Two-layer critical dimensions and overlay process window characterization and improvement in full-chip computational lithography;Journal of Micro/Nanolithography, MEMS, and MOEMS;2016-04-27

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