E-Test Validation of Space Error Budget and Metrology
Author:
Affiliation:
1. Advanced Patterning Department, Interuniversitair Microelectronica Centrum, Leuven, Belgium
2. Advanced Semiconductor Materials Lithography Netherlands B.V., Eindhoven, The Netherlands
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/66/9851188/09810988.pdf?arnumber=9810988
Reference18 articles.
1. Modeling edge placement error distribution in standard cell library
2. Single lithography exposure edge placement model;tyminski;Proc SPIE,2015
3. Measuring inter-layer edge placement error with SEM contours
4. Advanced CD-SEM solution for edge placement error characterization of BEOL pitch 32nm metal layers
5. Advanced CD-SEM imaging methodology for EPE measurements;takemasa;Proc SPIE,2018
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