Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes-Reference-Cited by-同舟云学术

Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

Published:2015-03-19 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Peterson Joel,Rusk Gary,Veeraraghavan Sathish,Huang Kevin,Koffas Telly,Kimani Peter,Sinha Jaydeep

Publisher

SPIE

Reference14 articles.

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2. International Technology Roadmap for Semiconductors, 2011 Edition, Table LITH2. http://www.itrs.net/Links/2012ITRS/2012Tables/Litho_2012Tables.xlsx

3. Mask-making, the most critical step in the new product introduction cycle;Chen,2012

4. Extending 1.35 NA immersion lithography down to 1x nm production nodes;Bouchoms,2012

5. High-order wafer alignment in manufacturing;Pike,2012

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