Overlay Control in HAR device integration
Author:
Affiliation:
1. Applied Materials,Santa Clara,USA
2. Applied Materials,Gloucester,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10145914/10145815/10145953.pdf?arnumber=10145953
Reference5 articles.
1. Lithography overlay control improvement using patterned wafer geometry for sub 22 nm technology nodes;peterson;Proc SPIE 9424 94240N,2015
2. How to improve overlay of highly deformed 3D NAND wafers;al;Proc SPIE 11326 113260M,2020
3. Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress
4. Intra-field stress impact on global wafer deformation
5. Measuring after-etch overlay and characterizing tilt fingerprints in multitier 3D-NAND structures;lee;Proc SPIE 10959 (2019) MOEMS 12 043002,2013
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1. CMOS Directly Bonded to Array (CBA) Technology for Future 3D Flash Memory;2023 International Electron Devices Meeting (IEDM);2023-12-09
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