The economic impact of EUV lithography on critical process modules

Author:

Mallik Arindam1,Horiguchi Naoto1,Bömmels Jürgen1,Thean Aaron1,Barla Kathy1,Vandenberghe Geert1,Ronse Kurt1,Ryckaert Julien1,Mercha Abdelkarim1,Altimime Laith1,Verkest Diederik1,Steegen An1

Affiliation:

1. IMEC (Belgium)

Publisher

SPIE

Reference15 articles.

1. PWC Corporation, “Faster, greener smarter: Reaching beyond the horizon in the world of semiconductors”, http://www.pwc.com/gx/en/technology/publications/semiconductor-industry-analysis-and-projections.jhtml

2. Cramming More Components onto Integrated Circuits;Moore,1965

3. FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

4. Method of manufacturing semiconductor local interconnect and contact;Yelehanka,2005

5. Neisser, Mark and Stefan Wurm. “ITRS lithography roadmap: status and challenges”, 1.4 (2012): 217–222. Retrieved 4 Feb. 2013, from doi:10.1515/aot-2012-0045

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