ASAP5: A predictive PDK for the 5 nm node

Author:

Vashishtha VinayORCID,Clark Lawrence T.ORCID

Funder

Defense Advanced Research Projects Agency

Publisher

Elsevier BV

Subject

General Engineering

Reference95 articles.

1. Vertically stacked gate-all-around Si nanowire transistors: key process optimizations and ring oscillator demonstration;Mertens,2017

2. Performance and design considerations for gate-all-around stacked-NanoWires FETs;Barraud,2017

3. High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor;Zhang,2017

4. Nanosheet field effect transistors-A next generation device to keep Moore's law alive: an intensive study;Ajayan;Microelectron. J.,2021

5. Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs;Huang;Microelectron. J.,2020

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1. On the SRAM with comb-shaped nano FETs advancing to 3 nm node and beyond;Microelectronics Journal;2023-08

2. Geometry Dependent Multi-stage Compact Thermal Model for Advanced Nanosheet FETs;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

3. NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-02

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