Geometry Dependent Multi-stage Compact Thermal Model for Advanced Nanosheet FETs
Author:
Affiliation:
1. School of Microelectronics Science and Technology, Sun Yat-sen University,Guangzhou,China,510275
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10218344/10218369/10218563.pdf?arnumber=10218563
Reference19 articles.
1. ASAP5: A predictive PDK for the 5 nm node
2. Geometrical influence on Self Heating in Nanowire and Nanosheet FETs using TCAD Simulations
3. Comparing bulk-Si FinFET and gate-all-around FETs for the 5 nm technology node
4. Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs
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1. A Neural Network-based Framework for Accelerated Device-Circuit Electrothermal Co-Simulations in GAAFETs;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10
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