Characterization and mitigation of overlay error on silicon wafers with nonuniform stress-Reference-Cited by-同舟云学术

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Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

Published:2014-03-31 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
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Author:

Brunner T.,Menon V.,Wong C.,Felix N.,Pike M.,Gluschenkov O.,Belyansky M.,Vukkadala P.,Veeraraghavan S.,Klein S.,Hoo C. H.,Sinha J.

Publisher

SPIE

Reference11 articles.

1. Extending immersion lithography down to 1x nm production nodes;de Boeij,2013

2. Overlay characterization and matching of immersion photoclusters;Minghetti,2010

3. Lens Heating Challenges for Negative Tone Develop Layers with Freeform Illumination;Halle,2012

4. Interferometry for wafer dimensional metrology;Freischlad,2007

5. Interferometry-based Characterization of Chip-Scale Topography for Advanced Semiconductor Nodes;Topaloglu,2013

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1. New wave front phase sensor used for 3D shape measurements of patterned silicon wafers;38th European Mask and Lithography Conference (EMLC 2023);2023-10-05

2. New metrology technique for measuring the free shape of a patterned 300mm wafer held vertically;Metrology, Inspection, and Process Control XXXVII;2023-04-27

3. Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions;Semiconductor Science and Technology;2021-12-21

4. What does the wolf eat? Assessing the diet of the endangered Iberian wolf (Canis lupus signatus) in northeast Portugal;PLOS ONE;2020-03-31

5. Comparison of processing-induced deformations of InP bonded to Si determined by e-beam metrology: Direct vs. adhesive bonding;Microelectronic Engineering;2019-06

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