The important challenge to extend spacer DP process towards 22nm and beyond

Author:

Oyama Kenichi,Nishimura Eiichi,Kushibiki Masato,Hasebe Kazuhide,Nakajima Shigeru,Murakami Hiroki,Hara Arisa,Yamauchi Shohei,Natori Sakurako,Yabe Kazuo,Yamaji Tomohito,Nakatsuji Ryota,Yaegashi Hidetami

Publisher

SPIE

Cited by 13 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Resolution Enhancement Techniques and Mask Data Preparation;Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology;2016-04-14

2. Cost effective processes by using negative-tone development application;Advances in Patterning Materials and Processes XXXII;2015-03-20

3. Sustainability and applicability of spacer-related patterning towards 7nm node;Advances in Patterning Materials and Processes XXXII;2015-03-20

4. Spectral analysis of the line-width and line-edge roughness transfer during self-aligned double patterning approach;SPIE Proceedings;2015-03-17

5. Innovative solutions on 193 immersion-based self-aligned multiple patterning;SPIE Proceedings;2014-03-27

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