Forbidden pitches: causes, source optimization, and their role in design rules
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SPIE
Reference13 articles.
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1. A Further Analysis of the Forbidden Pitch in Photolithography in Advanced Technology Nodes;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. Source optimization for forbidden pitch resolving in metal layer of 5nm technology node;DTCO and Computational Patterning;2022-05-26
3. Optimization of the EUV mask structures for mitigating the forbidden pitch in 5nm node;DTCO and Computational Patterning;2022-05-26
4. Analysis and mitigation of forbidden pitch effects for EUV lithography;Extreme Ultraviolet Lithography 2020;2020-09-20
5. Maskless EUV lithography, an alternative to e-beam;Journal of Micro/Nanolithography, MEMS, and MOEMS;2019-10-04
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