Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs-Reference-Cited by-同舟云学术

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Published:2016-03-16 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Huynh-Bao Trong,Ryckaert Julien,Sakhare Sushil,Mercha Abdelkarim,Verkest Diederik,Thean Aaron,Wambacq Piet

Publisher

SPIE

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