Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs
Author:
Affiliation:
1. Department of Electronic Engineering, Jinan University, Guangzhou 510630, China
Funder
National Natural Science Foundation of China (NSFC)
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://scitation.aip.org/deliver/fulltext/aip/journal/adva/4/8/1.4892609.pdf?itemId=/content/aip/journal/adva/4/8/10.1063/1.4892609&mimeType=pdf&containerItemId=content/aip/journal/adva
Reference15 articles.
1. Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness
2. High voltage characteristics of junctionless poly-silicon thin film transistors
3. Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an implant-free technique
4. Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
5. Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors
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