Author:
Su Chun-Jung,Tsai Tzu-I,Lin Horng-Chih,Huang Tiao-Yuan,Chao Tien-Sheng
Abstract
Abstract
In this work, we present a gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless device with TiN/Al2O3 gate stack using an implant-free approach. Since the source/drain and channel regions are sharing one in situ phosphorous-doped poly-Si material, the process flow and cost could be efficiently reduced. Owing to the GAA configuration and small volume of NW channels, the fabricated devices with heavily doped channels display superior switching behaviors and excellent immunity to short-channel effects. Besides, the negative fixed charges in Al2O3 are found to be helpful to obtain desirable positive threshold voltages for the n+-poly-Si channel devices. Thus, the simple and low-cost fabrication method along with excellent device characteristics makes the proposed GAA NW transistor a promising candidate for future 3-D electronics and system-on-panel applications.
Publisher
Springer Science and Business Media LLC
Subject
Condensed Matter Physics,General Materials Science
Reference12 articles.
1. Yeo KH, Suk SD, Li M, Yeoh YY, Cho KH, Hong KH, Yun S, Lee MS, Cho N, Lee K, Hwnag D, Park B, Kim DW, Park D, Ryu BI: Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In International Electron Devices Meeting: December 11–13 2006. IEEE, San Francisco. Piscataway; 2006:1–4.
2. Appenzeller J, Knoch J, Björk MT, Riel H, Schmid H, Riess W: Toward nanowire electronics. IEEE Trans Electron Devices 2008, 55: 2827.
3. Suk SD, Li M, Yeoh YY, Yeo KH, Ha JK, Lim H, Park HW, Kim DW, Chung TY, Oh KS, Lee WS: Characteristics of sub-5-nm trigate nanowire MOSFETs with single- and poly-Si channels in SOI structure. In VLSI Symposium Technology: June 16–18 2009; Honolulu. IEEE, Piscataway; 2009:142.
4. Singh N, Agarwal A, Bera LK, Liow TY, Yang R, Rustagi SC, Tung CH, Kumar R, Lo GQ, Balasubramanian N, Kwong DL: High-performance fully depleted silicon nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices. IEEE Electron Device Lett 2006, 27: 383.
5. Im M, Han JW, Lee H, Yu LE, Kim S, Kim CH, Jeon SC, Kim KH, Lee GS, Oh JS, Park YC, Lee HM, Choi YK: Multiple-gate CMOS thin-film transistor with polysilicon nanowire. IEEE Electron Device Lett 2008, 29: 102.
Cited by
8 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献