Bias temperature instability in metal-oxide-semiconductor field-effect transistors with atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics
Author:
Publisher
AIP Publishing
Subject
General Physics and Astronomy
Link
http://aip.scitation.org/doi/pdf/10.1063/1.2907768
Reference22 articles.
1. Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing
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3. Negative Bias Temperature Instability on Plasma-Nitrided Silicon Dioxide Film
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1. Positive bias temperature instability in p-type metal-oxide-semiconductor devices with HfSiON/SiO2 gate dielectrics;Journal of Applied Physics;2014-02-21
2. Effect of an Ultrathin SiN Cap Layer on the Bias Temperature Instability in Metal–Oxide–Semiconductor Field-Effect Transistors with HfSiON Gate Stacks;Japanese Journal of Applied Physics;2010-12-20
3. Effects of $\hbox{CF}_{4}$ Plasma Treatment on the Electrical Characteristics of Poly-Silicon TFTs Using a $ \hbox{Tb}_{2}\hbox{O}_{3}$ Gate Dielectric;IEEE Transactions on Electron Devices;2010-07
4. High-performance CF4 plasma treated polycrystalline silicon thin-film transistors using a high-k Tb2O3 gate dielectric;Applied Physics Letters;2010-03-15
5. Anomalous positive-bias temperature instability of high-κ/metal gate devices with Dy2O3 capping;Applied Physics Letters;2008-08-04
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