Review on impact of nanoscale on CMOS circuits in VLSI design-Reference-Cited by-同舟云学术

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Review on impact of nanoscale on CMOS circuits in VLSI design

Published:2021 Issue: Volume: Page:
ISSN:0094-243X
Container-title:SEVENTH INTERNATIONAL SYMPOSIUM ON NEGATIVE IONS, BEAMS AND SOURCES (NIBS 2020)
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Author:

Lakshminarayana Gajula,Sribindu S.,Suneel L.,Krishna S. Gopala

Publisher

AIP Publishing

Link

http://aip.scitation.org/doi/pdf/10.1063/5.0058029

Reference10 articles.

1. Umesh Jeevalu Chavan Siddarama R. Patil “High performance and Low power ONOFF IC Approach for VLSI CMOS circuits design” IEEE 2016

2. Preeti Verma “Estimation of Leakage power and Delay in CMOS circuits using parametric variation ELSEVIER-2016

3. Smita Singha, Nidhi Gaur, Anu Mehra and Pradeep Kumar, “Analysis and Comparison of Leakage Power Reduction Techniques in CMOS circuits,” 2015 2nd International Conference on Signal Processing and Integrated Networks(SPIN)

4. Prof. Ajit Pal “Low power VLSI circuit and System” ISBN 978-81-322-1937-8 (eBook) Springer India 2015.

5. TECHNIQUES FOR LOW LEAKAGE NANOSCALE VLSI CIRCUITS: A COMPARATIVE STUDY

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