Estimation of leakage power and delay in CMOS circuits using parametric variation

Author:

Verma Preeti,Sharma Ajay K.,Pandey Vinay Shankar,Noor Arti,Tanwar Anand

Publisher

Elsevier BV

Subject

General Engineering

Reference13 articles.

1. A minimum total power methodology for projecting limits on CMOS GSI;Bhavnagarwala;IEEE Trans. VLSI Syst.,2000

2. Minimizing power consumption in digital CMOS circuits;Chandrakasan;IEEE J. Solid-State Circuits,1999

3. Handling inverted temperature dependence in static timing analysis;dasdan,2006

4. Standby and active leakage current control and minimization in CMOS VLSI circuits;Fallah;IEICE Trans. Electron.,2005

5. Leakage power reduction using self bias transistor in VLSI circuits;Gopalakrishnan,2004

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