Charge trap flash memory using ferroelectric materials as a blocking layer
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4705411
Reference16 articles.
1. Direct Field Effect of Neighboring Cell Transistor on Cell-to-Cell Interference of nand Flash Cell Arrays
2. Transport mechanisms in atomic-layer-deposited Al2O3 dielectrics
3. Correlation between charge trap distribution and memory characteristics in metal/oxide/nitride/oxide/silicon devices with two different blocking oxides, Al2O3 and SiO2
4. A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (φ-Flash), suitable for full 3D integration
5. A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability
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