Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering-Reference-Cited by-同舟云学术

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

Published:2016-06-07 Issue:21 Volume:119 Page:214501
ISSN:0021-8979
Container-title:Journal of Applied Physics
language:en
Short-container-title:Journal of Applied Physics

Author:

Navlakha Nupur¹,Lin Jyi-Tsong²,Kranti Abhinav¹

Affiliation:

1. Low Power Nanoelectronics Research Group, Electrical Engineering Discipline, Indian Institute of Technology Indore, Simrol 452020, India

2. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung 80424, Taiwan

Funder

Department of Science and Technology, Government of India, through Global Innovation Technology Alliance (GITA)

Publisher

AIP Publishing

Subject

General Physics and Astronomy

Link

http://aip.scitation.org/doi/pdf/10.1063/1.4953086

Reference47 articles.

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