Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells
Author:
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.3494262
Reference13 articles.
1. DRAM technology perspective for gigabit era
2. Proceedings of the IEEE International SOI Conference;Okhonin S.,2001
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4. Characteristics of Fully Depleted Strained-Silicon-On-Insulator Capacitorless Dynamic Random Access Memory Cells
5. Proceedings of the IEEE International SOI Conference;Yu B.,1994
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1. Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors;IEEE Access;2023
2. Capacitor-less dynamic random access memory based on a III–V transistor with a gate length of 14 nm;Nature Electronics;2019-08-19
3. The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET;Nanoscale Research Letters;2017-09-06
4. Capacitorless single transistor dynamic random-access memory devices fabricated on silicon–germanium-on-insulator substrates;Thin Solid Films;2012-07
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