Effects of Interface States on Electrical Characteristics of Feedback Field-Effect Transistors
Author:
Affiliation:
1. Department of Electrical Engineering, Korea University, Seongbuk-gu, Seoul, Republic of Korea
Funder
National Research Foundation of Korea (NRF) grant funded by the Ministry of Science and ICT
Brain Korea 21 Plus Project and Samsung Electronics
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/10005208/10138580.pdf?arnumber=10138580
Reference24 articles.
1. Defect spectroscopy of sidewall interfaces in gate-all-around silicon nanosheet FET
2. NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors
3. Reliability Issues of In2O5Sn Gate Electrode Recessed Channel MOSFET: Impact of Interface Trap Charges and Temperature
4. Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors
5. Distribution of the energy levels of individual interface traps and a fundamental refinement in charge pumping theory
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1. Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability;Micro and Nanostructures;2024-07
2. Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels;Nanotechnology;2024-04-23
3. Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors;Nanomaterials;2024-03-23
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