Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability-Reference-Cited by-同舟云学术

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Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability

Published:2024-07 Issue: Volume:191 Page:207850
ISSN:2773-0123
Container-title:Micro and Nanostructures
language:en
Short-container-title:Micro and Nanostructures

Author:

Mudidhe Praveen Kumar^ORCID,Nistala Bheema Rao

Publisher

Elsevier BV

Reference39 articles.

1. Beyond the conventional transistor;Wong;Solid State Electron.,2005

2. Beyond Moore's law – a critical review of advancements in negative capacitance field effect transistors: a revolution in next-generation electronics;Valasa;Mater. Sci. Semicond. Process.,2024

3. Estimating the performance of SOI FinFET transistor using electro-thermal formulation in conjunction with the quasi-ballistic effective electron mobility approach;Nasri;Micro and Nanostructures,2022

4. Enhancement of a nanoscale novel esaki tunneling diode source TFET (ETDS-TFET) for low-voltage operations;Anvarifard;Silicon,2019

5. Multi-gate SOI MOSFETs;Colinge;Microelectron. Eng.,2007

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