Investigation of the thermal stability of Mo-In0.45Ga0.47As for applications as source/drain contacts

Author:

Walsh Lee A.1,Weiland Conan2,McCoy Anthony P.1,Woicik Joseph C.2,Lee Rinus T. P.3,Lysaght Pat3,Hughes Greg1

Affiliation:

1. Department of Physical Sciences, Dublin City University, Glasnevin, Dublin 9, Ireland

2. National Institute of Standards and Technology, Gaithersburg, Maryland 20899, USA

3. SEMATECH, 257 Fuller Road, Suite 2200, Albany, New York 12203, USA

Funder

Science Foundation Ireland (SFI)

U.S. Department of Energy (DOE)

Publisher

AIP Publishing

Subject

General Physics and Astronomy

Reference20 articles.

1. Chemical analysis of HfO2∕Si (100) film systems exposed to NH3 thermal processing

2. Y. T. Chen , J. Huang , J. Price , P. Lysaght , D. Veksler , C. Weiland , J. C. Woicik , G. Bersuker , R. Hill , J. Oh , P. D. Kirsch , R. Jammy , and J. C. Lee , “ III–V gate stack interface improvement to enable high mobility 11 nm node CMOS,” in 2012 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA) (2012), pp. 1–2.

3. J. Huang , N. Goel , P. Lysaght , D. Veksler , P. Nagaiah , S. Oktyabrsky , J. Price , H. Zhao , Y. T. Chen , J. C. Lee , J. C. Woicik , P. Majhi , P. D. Kirsch , and R. Jammy , “ Detailed high-k/In0.53Ga0.47As interface understanding to enable improved In0.53Ga0.47As gate stack quality,” in 2011 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) (2011), pp. 1–2.

4. Band alignment of atomic layer deposited HfO2 on clean and N passivated germanium surfaces

5. Initiation of a passivated interface between hafnium oxide and In(Ga)As(0 0 1)−(4×2)

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1. Understanding the factors affecting contact resistance in nanowire field effect transistors (NWFETs) to improve nanoscale contacts for future scaling;Journal of Applied Physics;2022-07-14

2. Analysis of Mo Sidewall Ohmic Contacts to InGaAs Fins;IEEE Transactions on Electron Devices;2021-10

3. NIST HAXPES at NSLS and NSLS-II;Synchrotron Radiation News;2018-07-04

4. Scaling Challenges for Advanced CMOS Devices;International Journal of High Speed Electronics and Systems;2017-02-17

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