Review of Four Improving Designs of Dynamic Latch Comparator-Reference-Cited by-同舟云学术

Review of Four Improving Designs of Dynamic Latch Comparator

Published:2023-04-13 Issue: Volume:44 Page:129-137
ISSN:2791-0210
Container-title:Highlights in Science, Engineering and Technology
language:
Short-container-title:HSET

Author:

Wang Sudong

Abstract

In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy efficiency. The overall performance of these comparators is evaluated in this paper.

Publisher

Darcy & Roy Press Co. Ltd.

Reference11 articles.

1. Amirkhan Dehkordi, Mehrdad, and Mehdi Dolatshahi. “An Energy-Efficient, 6 GS/s Dynamic Comparator in 90 Nm CMOS Technology.” Analog integrated circuits and signal processing 101.2 (2019): 319–330. Web.

2. Folla, J´erˆome K, et al. “A Low-offset Low-power and High-speed Dynamic Latch Comparator with a Preamplifier-enhanced Stage.” IET circuits, devices systems 15.1 (2021): 65–77. Web.

3. Huang, Zhengbo, and Hong Zhang. “Low-Voltage Bulk-Driven High-Speed Comparator for ADCs.” Electronics letters 55.13 (2019): 735–737. Web.

4. Canal, Bruno et al. “Low-Voltage Dynamic Comparator Using Positive Feedback Bulk Effect on a Floating Inverter Amplifier.” Analog integrated circuits and signal processing 108.3 (2021): 511–524. Web.

5. Wang, Yao et al. “A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage.” IEEE access 7 (2019): 93396–93403. Web.