A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage-Reference-Cited by-同舟云学术

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

Published:2020-12-17 Issue:1 Volume:15 Page:65-77
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Folla Jérôme K.¹²^ORCID,Crespo Maria L.²^ORCID,Wembe Evariste T.³^ORCID,Bhuiyan Mohammad A. S.⁴,Cicuttin Andres²,Essimbi Bernard Z.¹,Reaz Mamun B. I.⁵

Affiliation:

1. Department of Physics Laboratory of Energy Electrical and Electronics Systems University of Yaoundé I Yaoundé Cameroon

2. Multidisciplinary Laboratory (MLAB), International Centre for Theoretical Physics (ICTP) Trieste Italy

3. Department of Physics Laboratory of Electronics and Automatics University of Douala Douala Cameroon

4. Electrical and Electronics Engineering Xiamen University Malaysia Sepang Selangor Malaysia

5. Electrical, Electronic and Systems Engineering Universiti Kebangsaan Malaysia Bangi Selangor Malaysia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/cds2.12008

Reference32 articles.

1. A novel high-speed low-power dynamic comparator with complementary differential input in 65 nm CMOS technology

2. Design of low power comparator-reduced hybrid ADC

3. Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load

4. A low-power low-offset dynamic comparator for analog to digital converters

5. Design and analysis of low power and high speed dynamic latch comparator in 0.18μm CMOS process;Raja M.;Int. J. Info Elec. Eng.,2012

Cited by 22 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications;Circuits, Systems, and Signal Processing;2024-08-13

2. CMOS readout FEE based TV-BLR module for CdZnTe pixel detectors in high count rate applications;Ain Shams Engineering Journal;2024-01

3. Design and analyze output power of two bit magnitude comparator using NMOS logic compared with CMOS logic;AIP Conference Proceedings;2024

4. Design of low power dynamic comparator with reduced kickback noise technique for bio-medical applications;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2023-12

5. A Post-Silicon Validation Method for Low-Power 180 nm Dynamic Comparator in Differential 10-bit SAR ADC;2023 IEEE 9th International Conference on Smart Instrumentation, Measurement and Applications (ICSIMA);2023-10-17