A Low-Power High-Speed Dynamic Comparator With a Transconductance-Enhanced Latching Stage

Author:

Wang YaoORCID,Yao Mengmeng,Guo Benqing,Wu Zhaolei,Fan Wenbing,Liou Juin Jei

Funder

National Natural Science Foundation of China

Science and Technology Project of Henan Province

Zhengzhou University

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science

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3. Design and Analysis of Different 2-Stage Dynamic Comparators for Low Power Consumption and High Speed;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

4. Low Power High Speed Inverter Based Differential Input Dynamic Comparator;2024 16th International Conference on Electronics, Computers and Artificial Intelligence (ECAI);2024-06-27

5. A high‐speed and power efficient CMOS dynamic comparator for data converter circuits;International Journal of Numerical Modelling: Electronic Networks, Devices and Fields;2024-06-26

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