Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications-Reference-Cited by-同舟云学术

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Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications

Published:2024-01-20 Issue:2 Volume:25 Page:218-231
ISSN:1229-7607
Container-title:Transactions on Electrical and Electronic Materials
language:en
Short-container-title:Trans. Electr. Electron. Mater.

Author:

Sarangam K.,Kumar Aruru Sai^ORCID,Reddy B. Naresh Kumar

Publisher

Springer Science and Business Media LLC

Link

https://link.springer.com/content/pdf/10.1007/s42341-023-00503-2.pdf

Reference42 articles.

1. B. Razavi, B.A. Wooley, Design techniques for high-speed, high-resolution comparators. IEEE J. Solid State Circuits 27(12), 1916–1926 (1992). https://doi.org/10.1109/4.173122

2. P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design (Oxford University Press, Oxford, 2002)

3. K. Dubey Avaneesh, R.K. Nagaria, Enhanced gain low-power CMOS amplifiers: a novel design approach using bulk-driven load and introduction to GACOBA technique. J Circuit Syst Comput 27(13), 1850204 (2018). https://doi.org/10.1142/S0218126618502043

4. B. Goll, H. Zimmermann, A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65 V. IEEE Trans. Circuits Syst. II Express Briefs 56(11), 810–814 (2009). https://doi.org/10.1109/TCSII.2009.2030357

5. B. Wicht, T. Nirschl, L. Schmitt, D. Siedel, Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J. Solid State Circuits 39, 1148–1158 (2004)

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Shift Registers Using DG-FinFET for Low Power Applications;2024 7th International Conference on Devices, Circuits and Systems (ICDCS);2024-04-23

2. A Novel Design of High Performance Two-Stage Operational Amplifier using CMOS Technology;2024 International Conference on Integrated Circuits and Communication Systems (ICICACS);2024-02-23

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