Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip-Reference-Cited by-同舟云学术

Layout Synthesis Design Flow for Special-Purpose Reconfigurable Systems-on-a-Chip

Published:2019-05 Issue:3 Volume:48 Page:176-186
ISSN:1063-7397
Container-title:Russian Microelectronics
language:en
Short-container-title:Russ Microelectron

Author:

Gavrilov S. V.,Zheleznikov D. A.,Zapletina M. A.,Khvatov V. M.,Chochaev R. Zh.,Enns V. I.

Publisher

Pleiades Publishing Ltd

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://link.springer.com/content/pdf/10.1134/S1063739719030053.pdf

Reference24 articles.

1. Gavrilov, S.V., Metody analiza logicheskikh korrelyatsii dlya SAPR tsifrovykh KMOP SBIS (Methods of Analysis of Logical Correlations in CAD for Digital CMOS VLSI), Moscow: Tekhnosfera, 2011.

2. Yosys Open Synthesis Suite. Version 0.8. http://www.clifford.at/yosys/.

3. ABC: A System for Sequential Synthesis and Verification. Berkeley Logic Synthesis and Verification Group. https://people.eecs.berkeley.edu/~alanmi/abc/.

4. Kernighan, B.W. and Lin, S., An efficient heuristic procedure for partitioning graphs, Bell Syst. Tech. J., 1970, vol. 49, no. 2, pp. 291–307.

5. Fiduccia, C.M. and Mattheyses, R.M., A linear-time heuristic for improving network partitions, in Proceedings of the 19th Design Automation Conference DAC, Las Vegas, NV, 1982, pp. 175–181.

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