Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs
Author:
Publisher
Pleiades Publishing Ltd
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1134/S106373972207006X.pdf
Reference13 articles.
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2. Vasilyev, N.O., Tiunov, I.V., and Ryzhova, D.I., The simulated annealing based logical resynthesis method for lut-based FPGAs, in Proceedings of the 2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), Moscow: IEEE, 2020, pp. 1892–1894. https://doi.org/10.1109/EIConRus49466.2020.9038959
3. Ziener, D., Assmus, S., and Teich, J., Identifying FPGA IP-cores based on lookup table content analysis, in Proceedings of the 2006 International Conference on Field Programmable Logic and Applications, Madrid: IEEE, 2006, pp. 1–6. https://doi.org/10.1109/FPL.2006.311255
4. Shubnaya, A. and Shupletsov, M., Algorithms for ip block identification based on structural approach, in Proceedings of the 2019 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus), St. Petersburg: IEEE, 2019, pp. 1672–1677. https://doi.org/10.1109/EIConRus.2019.8656919
5. Frolova, P.I., Chochaev, R.Zh., Ivanova, G.A., and Gavrilov, S.V., Timing-driven placement algorithm based on delay matrix model for reconfigurable system-on-chip, Probl. Razrab. Persp. Mikro- Nanoelektron. Sist., 2020, no. 1, pp. 2–7. https://doi.org/10.31114/2078-7707-2020-1-2-7
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