Pathfinder Algorithm Modification for FPGA Routing Stage
Author:
Publisher
Pleiades Publishing Ltd
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1134/S1063739722070125.pdf
Reference23 articles.
1. McMurchie, L. and Ebeling, C., PathFinder: A negotiation-based performance-driven router for FPGAs, in FPGA’95: Proceedings of the 1995 ACM 3rd International Symposium on Field-Programmable Gate Arrays, New York: ACM, 1995, pp. 111–117. https://doi.org/10.1145/201310.201328
2. Zhou, Y., Vercruyce, D., and Stroobandt, D., Accelerating FPGA routing through algorithmic enhancements and connection-aware parallelization, ACM Trans. Reconfig. Technol. Syst., 2020, vol. 13, no. 4, p. 18. https://doi.org/10.1145/3406959
3. Murray, K.E., Petelin, O., Zhong, Sh., et al., VTR 8: High-performance CAD and customizable FPGA architecture modelling, ACM Trans. Reconfig. Technol. Syst., 2020, vol. 13, no. 2, p. 9. https://doi.org/10.1145/3388617
4. Pan, M., Xu, Y., Zhang, Y., and Chu, Ch., Fastroute: An efficient and high-quality global router, VLSI Design, 2012, vol. 2012, p. 608362. https://doi.org/10.1155/2012/608362
5. He, J., Burtscher, M., Manohar, R., and Pingali, K., SPRoute: A scalable parallel negotiation-based global router, in Proceedings of the 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2019), Westminster, CO: IEEE, 2019, pp. 1–8. https://doi.org/10.1109/ICCAD45719.2019.8942105
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