FastRoute: An Efficient and High-Quality Global Router

Author:

Pan Min1,Xu Yue2,Zhang Yanheng3,Chu Chris2

Affiliation:

1. Synopsys Inc., Mountain View, CA 94043, USA

2. Department of Electrical and Computer Engineering, Iowa State University, Ames, IA 50011, USA

3. Cadence Design Systems Inc., San Jose, CA 95134, USA

Abstract

Modern large-scale circuit designs have created great demand for fast and high-quality global routing algorithms to resolve the routing congestion at the global level. Rip-up and reroute scheme has been employed by the majority of academic and industrial global routers today, which iteratively resolve the congestion by recreating the routing path based on current congestion. This method is proved to be the most practical routing framework. However, the traditional iterative maze routing technique converges very slowly and easily gets stuck at local optimal solutions. In this work, we propose a very efficient and high-quality global router—FastRoute. FastRoute integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3-bend routing, virtual capacity adjustment, multisource multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient to solve ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers.

Publisher

Hindawi Limited

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Hardware and Architecture

Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route;ACM Transactions on Design Automation of Electronic Systems;2023-12-18

2. Pathfinder Algorithm Modification for FPGA Routing Stage;Russian Microelectronics;2022-12

3. RosettaStone: Connecting the Past, Present, and Future of Physical Design Research;IEEE Design & Test;2022-10

4. From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction;Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD;2022-09-12

5. From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction;2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD);2022-09-12

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