From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction
Author:
Affiliation:
1. University of Minnesota,Minneapolis,MN,USA
2. University of California,San Diego,CA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9900062/9900076/09900099.pdf?arnumber=9900099
Reference18 articles.
1. Fast and Accurate Wire Timing Estimation on Tree and Non-Tree Net Structures
2. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
3. 2019 CAD Contest: LEF/DEF Based Global Routing
4. A timing engine inspired graph neural network model for pre-routing slack prediction
5. Accurate timing prediction at placement stage with look-ahead RC network
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1. A Deep Learning Model for Pre-Routing Path Delay Prediction in VLSI Based on Subpath;2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE);2024-05-24
2. Edge-weighted Graph Neural Networks for Post-placement Interconnect Capacitance Estimation of Analog Circuits;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25
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