Solving the FPGA Routing Problem Using the Model of an Extended Mixed Routing Graph
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Published:2023-12
Issue:7
Volume:52
Page:682-689
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ISSN:1063-7397
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Container-title:Russian Microelectronics
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language:en
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Short-container-title:Russ Microelectron
Publisher
Pleiades Publishing Ltd
Reference19 articles.
1. Wu, Y.-L. and Chang, D., On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution, IEEE/ACM Int. Conf. on Computer-Aided Design, San Jose, Calif., 1994, IEEE, 1994, pp. 362–366. https://doi.org/10.1109/ICCAD.1994.629819 2. Vercruyce, D., Vansteenkiste, E., and Stroobandt, D., CRoute: A fast high-quality timing-driven connection-based FPGA router, 2019 IEEE 27th Annu. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), San Diego: Calif., 2019, IEEE, 2019, pp. 53–60. https://doi.org/10.1109/FCCM.2019.00017 3. Murray, K.E., Zhong, S., and Betz, V., AIR: A fast but lazy timing-driven FPGA router, 25th Asia and South Pacific Design Automation Conf. (ASP-DAC), Beijing, 2020, IEEE, 2020, pp. 338–344. https://doi.org/10.1109/ASP-DAC47756.2020.9045175 4. Murray, K.E., Petelin, O., Zhong, Sh., Wang, J.M., Eldafrawy, M., Legault, J.-Ph., Sha, E., Graham, A.G., Wu, J., Walker, M.J.P., Zeng, H., Patros, P., Luu, J., Kent, K.B., and Betz, V., VTR 8: High-performance CAD and customizable FPGA architecture modeling, ACM Trans. Reconfigurable Technol. Syst., 2020, vol. 13, no. 2, pp. 1–55. https://doi.org/10.1145/3388617 5. Zapletina, M.A., Methods for speeding up the modified pathfinder routing algorithm for island-style FPGA, Probl. Razrab. Perspektivnykh Mikro- Nanoelektronnykh Sistem, 2021, no. 4, pp. 27–33. https://doi.org/10.31114/2078-7707-2021-4-27-33
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