Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET-Reference-Cited by-同舟云学术

Performance Analysis of Various Fin Patterns of Hybrid Tunnel FET

Published:2022-12-30 Issue:4 Volume:10 Page:806-810
ISSN:2347-470X
Container-title:International Journal of Electrical and Electronics Research
language:en
Short-container-title:IJEER

Author:

Dharmireddy Ajay Kumar¹,Ijjada Dr Sreenivasa Rao²,Latha Dr I. Hema³

Affiliation:

1. Research scholar, Department of Electronics & Communication Engineering, GITAM Deemed to be University, Vishakhapatnam, India

2. Assistant Professor, Department of Electronics & Communication Engineering, GITAM Deemed to be University, Vishakhapatnam, India

3. Associate Professor, Department of Electronics & Communication Engineering, Sir C. R. Reddy College of Engineering, Eluru, Andhra Pradesh, India

Abstract

High speed and low power dissipation devices are expected from future generation technology of Nano-electronic devices. Tunnel field effect transistor (TFET) technology is unique to the prominent devices in low power applications. To minimize leakage currents, the tunnel switching technology of TFETs is superior to conventional MOS FETs. The gate coverage area of different fin shape hybrid tunnel field-effect transistors is more impacted on electric characteristics of drive current, leakage current and subthreshold slope. In this paper design various fin patterns of hybrid TFET devices and shows on better performance as compared with other fin shape hybrid tunnel FET. The TCAD simulation tool is used to determine the characteristics of different fin shape tunnel FET.

Publisher

FOREX Publication

Subject

Electrical and Electronic Engineering,Engineering (miscellaneous)

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