Affiliation:
1. Department of Electronics and Communication Engineering, GITAM (Deemed to be University), Visakhapatnam, India
Abstract
Tunnel field effect transistor (TFET) technology is unique of the prominent devices in low power applications. The band-to-band tunnel switching mechanism is sets TFET apart from traditional MOSFET technology. It helps to reduce leakage currents. The major advantage is the Sub threshold slope smaller than 60mv/decade. Newer technologies are expected to change the gate, architectures, channel materials and transport mechanisms. In this point of view tunnel FET has to play the most imminent role in the least leakage current and also need to overcome limitations of drive current in TFET. The proposed model of hetero junction double gate TFET has attain superior ON state current, low off-state current and better steeper slope i.e., 4.94 x10-5A/µm, 32.3 x10-17A/µm 28.3mv/decade as compared with single gate hetero junction TFET and conventional device. This proposed design suitable for high switching speed and low power application.
Subject
Electrical and Electronic Engineering,Engineering (miscellaneous)
Reference22 articles.
1. Matthias Schmidt, Anna Schäfer, Renato A. Minamisawa, Dan Buca, Stefan Trellenkamp, Jean-Michel Hartmann, Qing-Tai Zhao, and Siegfried Mantl, “Line and Point Tunneling in Scaled Si/SiGeHeterostructure TFETs” IEEE Electron Device Letters, Vol. 35, No. 7, July 2014.
2. D.A.kumar , M. S.Babu, S.RaoIjjada. "SS < 30 mV/dec; Hybrid tunnel FET 3D analytical model for IoT applications", Materials Today: Proceedings, Nov. 2020.
3. AbhishekAcharya ,SudebDasgupta and BulusuAnand “A novel VDSAT extraction method for tunnel FETs and its implication on analogDesign”IEEE Transactions On Electron Devices, Vol. 64, No. 2,pp. 629-633, February 2017..
4. Anjana Devi N, Kumar DA “Doping and Dopingless III-V Tunnel FETs:Investigations on reasons for ON-current improvement” International Conference on Recent challenges in Engineering science and Technology,2021.
5. DharmireddyAjaykumar, ISR, Murthy P.H.S.T, “performance analysis of Tri-gate SOI FinFET structure with various fin heights using TCAD simulations”, JARDCS,Vol-11(2)pp-1291-1298,2019.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献