Design and Implementation of a Bootstrap-based Sample and Hold Circuit for SAR ADC Applications

Abstract

The resolution and conversion speed of an Analog to Digital converter (ADCs) strongly depends on how efficiently Sampling and Hold (S&H) circuit handles the amplitude skewing of the input analog signal. In this article, a novel S&H circuit has been proposed to handle the errors produced because of amplitude skewing. This circuit has two different paths for sampling and holds process and avoids the non-ideal effects seen in most of the recent literature. In portable applications, the restrictions on the available power and the importance of the quality of digital data are taken as a challenge. To make SAR-ADC more power efficient, all blocks should be designed with low-power techniques. Here, the sample and hold block need to be designed to the optimized power level, operate supply of 3.3V, implemented with SCL 0.18µm process, operating at a sampling rate of 10MHz with the power of 0.425mW.