Low Contact Resistance on Monolayer MoS<sub>2</sub> Field-Effect Transistors Achieved by CMOS-Compatible Metal Contacts-Reference-Cited by-同舟云学术

Low Contact Resistance on Monolayer MoS₂ Field-Effect Transistors Achieved by CMOS-Compatible Metal Contacts

Published:2024-08-07 Issue:33 Volume:18 Page:22444-22453
ISSN:1936-0851
Container-title:ACS Nano
language:en
Short-container-title:ACS Nano

Author:

Sun Zheng¹²^ORCID,Kim Seong Yeoul³,Cai Jun¹²^ORCID,Shen Jianan⁴^ORCID,Lan Hao-Yu¹²,Tan Yuanqiu¹²,Wang Xinglu³^ORCID,Shen Chao⁴,Wang Haiyan¹⁴^ORCID,Chen Zhihong¹²,Wallace Robert M.³^ORCID,Appenzeller Joerg¹²

Affiliation:

1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, United States

2. Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, United States

3. Department of Materials Science and Engineering, University of Texas at Dallas, Richardson, Texas 75080, United States

4. School of Materials Engineering, Purdue University, West Lafayette, Indiana 47907, United States

Funder

National Institute of Standards and Technology

Intel Corporation

Office of Naval Research

Division of Materials Research

Publisher

American Chemical Society (ACS)

Link

https://pubs.acs.org/doi/pdf/10.1021/acsnano.4c07267

Reference41 articles.

1. Chung, Y.Y.; Yun, W.S.; Chou, B.J.; Hsu, C.F.; Yu, S.M.; Arutchelvan, G.; Li, M.Y.; Lee, T.E.; Lin, B.J.; Li, C.Y.; Wei, A.; Sathaiya, D. M.; Chung, C.T.; Liew, S.L.; Hou, V. D.H.; Chang, W.H.; Liu, B.H.; Chen, C.W.; Su, C.Y.; Kei, C.C.; Cai, J.; Wu, C.C.; Wu, J.; Lee, T.Y.; Chien, C.H.; Cheng, C.C.; Radu, I. P. Monolayer-MoS2 Stacked Nanosheet Channel with C-Type Metal Contact. In 2023 International Electron Devices Meeting (IEDM), 2023; pp 1–4.

2. Dorow, C. J.; Schram, T.; Smets, Q.; O’Brien, K. P.; Maxey, K.; Lin, C.C.; Panarella, L.; Kaczer, B.; Arefin, N.; Roy, A.; Jordan, R.; Oni, A.; Penumatcha, A.; Naylor, C. H.; Kavrik, M.; Cott, D.; Graven, B.; Afanasiev, V.; Morin, P.; Asselberghs, I.; Lockhart de La Rosa, C. J.; Sankar Kar, G.; Metz, M.; Avci, U. Exploring Manufacturability of Novel 2D Channel Materials: 300 Mm Wafer-Scale 2D NMOS & PMOS Using MoS2, WS2, & WSe2. In 2023 International Electron Devices Meeting (IEDM), 2023; pp 1–4.

3. Chou, A.S.; Hsu, C.H.; Lin, Y.T.; Arutchelvan, G.; Chen, E.; Hung, T. Y. T.; Hsu, C.F.; Chou, S.A.; Lee, T.E.; Madia, O.; Doornbos, G.; Su, Y.C.; Azizi, A.; Sathaiya, D. M.; Cai, J.; Wang, J.F.; Chung, Y.Y.; Wu, W.C.; Neilson, K.; Yun, W.S.; Hsu, Y.W.; Hsu, M.C.; Hou, F.R.; Shen, Y.Y.; Chien, C.H.; Wu, C.C.; Wu, J.; Wong, H.S. P.; Chang, W.H.; van Dal, M.; Cheng, C.C.; Wu, C.I.; Radu, I. P. Status and Performance of Integration Modules Toward Scaled CMOS with Transition Metal Dichalcogenide Channel. In 2023 International Electron Devices Meeting (IEDM), 2023; pp 1–4.

4. Statistical Assessment of High-Performance Scaled Double-Gate Transistors from Monolayer WS₂

5. High Performance Multilayer MoS2 Transistors with Scandium Contacts